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參數(shù)資料
| 型號： | SNJ54LV165AW |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | PARALLEL-LOAD 8-BIT SHIFT REGISTERS |
| 中文描述： | 并行-載重8位轉(zhuǎn)換寄存器 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 472K |
| 代理商： | SNJ54LV165AW |
SCLS402K APRIL 1998 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock
inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a
low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only
while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are
enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OPERATION
SH/LD
CLK
CLK INH
L
X
X
Parallel load
H
H
X
Q0
Q0
Shift
H
X
H
↑
L
H
L
↑
H
Shift
logic diagram (positive logic)
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
QH
QH
11
12
13
14
3
4
5
6
A
B
C
D
E
F
G
H
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
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