參數(shù)資料
型號: SN75LVDS83BZQLR
廠商: Texas Instruments
文件頁數(shù): 1/30頁
文件大?。?/td> 0K
描述: IC FLATLINK XMITTER 56BGA
標(biāo)準(zhǔn)包裝: 1
系列: FlatLink™
類型: 發(fā)射器
驅(qū)動器/接收器數(shù): 5/0
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 56-VFBGA
供應(yīng)商設(shè)備封裝: 56-BGA MICROSTAR JUNIOR(7.0x4.5)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 907 (CN2011-ZH PDF)
其它名稱: 296-24530-6
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SN75LVDS83B
FlatLink Transmitter
TM
PackageOptions
TSSOP:8x14mmDGG
BGA:4.5x7mm
Application
processor
(e.g.OMAP )
TM
SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011
FLATLINK TRANSMITTER
Check for Samples: SN75LVDS83B
1
FEATURES
Voltage Differential
Consumes Less Than 1mW When Disabled
2
LVDS Display Serdes Interfaces Directly to
LCD Display Panels with Integrated LVDS
Selectable Rising or Falling Clock Edge
Triggered Inputs
Package Options: 4.5mm x 7mm BGA, and
8.1mm x 14mm TSSOP
ESD: 5kV HBM
1.8V up to 3.3V Tolerant Data Inputs to
Support Spread Spectrum Clocking (SSC)
Connect Directly to Low-Power, Low-Voltage
Compatible with all OMAP2x, OMAP3x,
Application and Graphic Processors
and DaVinci Application Processors
Transfer Rate up to 135Mpps (Mega Pixel Per
Second); Pixel Clock Frequency Range 10MHz
APPLICATIONS
to 135MHz
LCD Display Panel Driver
Suited for Display Resolutions Ranging From
UMPC and Netbook PC
HVGA up to HD With Low EMI
Digital Picture Frame
Operates From a Single 3.3V Supply and
170mW (typ.) at 75MHz
28 Data Channels Plus Clock In Low-Voltage
TTL to 4 Data Channels Plus Clock Out Low-
DESCRIPTION
The SN75LVDS83B FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock
synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair
conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS
receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The
frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and
serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.
The frequency of CLKOUT is the same as the input clock, CLKIN.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
OMAP, DaVinci, FlatLink are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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