參數(shù)資料
型號(hào)： SN75976ADL
廠商： Texas Instruments, Inc.
英文描述： 12-Bit 250kHz CMOS Analog-to-Digital Converter w/Serial Interface 2.5V Internal Reference 20-SOIC -40 to 85
中文描述： 9通道差分收發(fā)器
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 459K
代理商： SN75976ADL
SN75976A, SN55976A
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS218B – MAY 1995 – REVISED MAY 1997
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
SN75976A
MIN
TYP
2.5
UNIT
MAX
13.5
ns
’976A1
VCC = 5 V,
VCC = 5 V,
TC = 25
°
C
TC = 100
°
C
3
11
ns
td
tpd
Propagation delay time,PHL
(see Figures 1 and 2)
5
13
ns
PLH
4.5
11.5
ns
’976A2
VCC = 5 V,
VCC = 5 V,
TC = 25
°
C
TC = 100
°
C
5
9
ns
7
11
ns
tk(li )
tsk(lim)
Skew limit, maximum tpd
(see Note 5)
’976A1
8
ns
d
’976A2
4
ns
tsk(p)
tf
tr
ten
tdis
tPHZ
tPLZ
tPZH
tPZL
All typical values are at VCC = 5 V, TA = 25
°
C.
NOTE 5: This parameter is applicable at one VCC and operating temperature within the recommended operating conditions and to any two
devices.
Pulse skew, |tPHL – tPLH|
Fall time
4
ns
S1 to B,
See Figure 2
4
ns
Rise time
See Figure 2
8
ns
Enable time, control inputs to active output
50
ns
Disable time, control inputs to high-impedance output
100
ns
Propagation delay time, high-level to high-impedance output
17
100
ns
Propagation delay time, low-level to high-impedance output
See Figures 5 and 6
25
100
ns
Propagation delay time, high-impedance to high-level output
17
50
ns
Propagation delay time, high-impedance to low-level output
17
50
ns
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
SN55976A
MIN
TYP
UNIT
MAX
td
tpd
Propagation delay time,PHL
(see Figures 1 and 2)
’976A1
VCC = 5 V,
VCC = 5 V,
TA = 25
°
C
TA = 25
°
C
15
ns
PLH
’976A2
13.5
ns
tk(li )
tsk(lim)
Skew limit, maximum tpd
(see Note 5)
’976A1
8
ns
d
’976A2
4
ns
tsk(p)
tf
tr
ten
tdis
tPHZ
tPLZ
tPZH
tPZL
All typical values are at VCC = 5 V, TA = 25
°
C.
NOTE 5. This parameter is applicable at one VCC and operating temperature within the recommended operating conditions and to any two
devices.
Pulse skew, |tPHL – tPLH|
Fall time
4
ns
S1 to B,
See Figure 2
4
ns
Rise time
See Figure 2
8
ns
Enable time, control inputs to active output
60
ns
Disable time, control inputs to high-impedance output
Propagation delay time, high-level to high-impedance output
140
120
ns
ns
Propagation delay time, low-level to high-impedance output
See Figures 5 and 6
120
ns
Propagation delay time, high-impedance to high-level output
60
ns
Propagation delay time, high-impedance to low-level output
60
ns
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