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參數(shù)資料
| 型號： | SN75976ADL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-Bit 250kHz CMOS Analog-to-Digital Converter w/Serial Interface 2.5V Internal Reference 20-SOIC -40 to 85 |
| 中文描述： | 9通道差分收發(fā)器 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 459K |
| 代理商： | SN75976ADL |
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SN75976A, SN55976A
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS218B – MAY 1995 – REVISED MAY 1997
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 2. Typical Signal and Terminal Assignments
SIGNAL
TERMINAL
SCSI DATA
SCSI CONTROL
IPI DATA
IPI CONTROL
CDE0
54
DIFFSENSE
DIFFSENSE
VCC
XMTA, XMTB
VCC
GND
CDE1
55
GND
GND
CDE2
56
GND
GND
XMTA, XMTB
SLAVE/MASTER
BSR
2
GND
GND
GND, BSR
GND
CRE
3
GND
GND
GND
VCC
NOT USED
1A
4
DB0, DB8
ATN
AD7, BD7
1DE/RE
5
DBE0, DBE8
INIT EN
GND
GND
2A
6
DB1, DB9
BSY
AD6, BD6
NOT USED
2DE/RE
7
DBE1, DBE9
BSY EN
GND
GND
3A
8
DB2, DB10
ACK
AD5, BD5
SYNC IN
3DE/RE
9
DBE2, DBE10
INIT EN
GND
GND
4A
10
DB3, DB11
RST
AD4, BD4
SLAVE IN
4DE/RE
11
DBE3, DBE11
GND
GND
GND
5A
19
DB4, DB12
MSG
AD3, BD3
NOT USED
5DE/RE
20
DBE4, DBE12
TARG EN
GND
GND
6A
21
DB5, DB13
SEL
AD2, BD2
SYNC OUT
6DE/RE
22
DBE5, DBE13
SEL EN
GND
GND
7A
23
DB6, DB14
C/D
AD1, BD1
MASTER OUT
7DE/RE
24
DBE6, DBE14
TARG EN
GND
GND
8A
25
DB7, DB15
REQ
AD0, BD0
SELECT OUT
8DE/RE
26
DBE7, DBE15
TARG EN
GND
GND
9A
27
DBP0, DBP1
I/O
AP, BP
ATTENTION IN
9DE/RE
28
DBPE0, DBPE1
TARG EN
XMTA, XMTB
VCC
ABBREVIATIONS:
DBn = data bit n, where n = (0,1, . . . ,15)
DBEn = data bit n enable, where n = (0,1, . . . ,15)
DBP0 = parity bit for data bits 0 through 7 or IPI bus A
DBPE0 = parity bit enable for P0
DBP1 = parity bit for data bits 8 through 15 or IPI bus B
DBPE1 = parity bit enable for P1
ADn or BDn = IPI Bus A – Bit n (ADn) or Bus B – Bit n (BDn), where n = (0,1, . . . ,7)
AP or BP = IPI parity bit for bus A or bus B
XMTA or XMTB = transmit enable for IPI bus A or B
BSR = bit significant response
INIT EN = common enable for SCSI initiator mode
TARG EN = common enable for SCSI target mode
NOTE A: Signal inputs are shown as active high. When only active-low inputs are available, logic inversion
is accomplished by reversing the B+ and B– connector terminal assignments.
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