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參數(shù)資料
| 型號(hào)： | SN74SSTU32864CGKER |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL 18 INPUTS AND OUTPUTS |
| 中文描述： | 25位可配置注冊(cè)緩沖區(qū)薩里衛(wèi)星技術(shù)有限公司18輸入和輸出 |
| 文件頁(yè)數(shù)： | 1/18頁(yè) |
| 文件大?。?/td> | 304K |
| 代理商： | SN74SSTU32864CGKER |
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www.ti.com
FEATURES
Member of the Texas Instruments Widebus+
Family
Pinout Optimizes DDR2 DIMM PCB Layout
Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
Chip-Select Inputs Gate Data Outputs From
Changing State and Minimize System Power
Consumption
Output Edge-Control Circuitry Minimizes
Switching Noise in Unterminated Line
Supports SSTL_18 Data Inputs
DESCRIPTION/ORDERING INFORMATION
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V
CC
operation. In the 1:1
pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive 18 SDRAM loads.
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on
Control and RESET Inputs
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to
14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to
a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the
A6, D6, and H6 terminals are driven low and should not be used.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is
cleared and the data outputs are driven low quickly, relative to the time to disable the differential input receivers.
However, when coming out of reset, the register becomes active quickly, relative to the time required to enable
the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the
low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTU32864C
must ensure that the outputs remain low, thus ensuring no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
SN74SSTU32864CGKER
SN74SSTU32864CZKER
TOP-SIDE MARKING
S864C
S864C
LFBGA – GKE
LFBGA – ZKE
Tape and reel
Tape and reel
0
°
C to 70
°
C
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2004–2005, Texas Instruments Incorporated
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74SSTU32864CZKER | 功能描述:緩沖器和線路驅(qū)動(dòng)器 25-Bit Configurable Registered Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74SSTU32864DGKER | 功能描述:緩沖器和線路驅(qū)動(dòng)器 25-Bit Configurable Registered Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74SSTU32864DZKER | 功能描述:緩沖器和線路驅(qū)動(dòng)器 25-Bit Configurable Registered Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74SSTU32864EZKER | 功能描述:寄存器 25-Bit Configurable Registered Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SN74SSTU32864GKER | 功能描述:緩沖器和線路驅(qū)動(dòng)器 Single-Supply Voltage Translator RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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