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參數(shù)資料
| 型號： | SN74SSTU32866GKER |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST |
| 中文描述： | 25位可配置注冊緩沖區(qū)地址平價試驗 |
| 文件頁數(shù)： | 1/37頁 |
| 文件大?。?/td> | 725K |
| 代理商： | SN74SSTU32866GKER |
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SCES564 APRIL 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus+
Family
Pinout Optimizes DDR2 DIMM PCB Layout
Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
Chip-Select Inputs Gate the Data Outputs
from Changing State and Minimizes System
Power Consumption
Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
Supports SSTL_18 Data Inputs
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the
Control and RESET Inputs
Checks Parity on DIMM-Independent Data
Inputs
Able to Cascade with a Second
SN74SSTU32866
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low, Except QERR
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
description/ordering information
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V
CC
operation. In the
1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the
open-drain error (QERR) output.
The SN74SSTU32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The SN74SSTU32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,
compares it with the data received on the DIMM-independent D-inputs (D2D3, D5D6, D8D25 when
C0 = 0 and C1 = 0; D2D3, D5D6, D8D14 when C0 = 0 and C1=1; or D1D6, D8D13 when C0 = 1 and
C1=1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The
convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent
data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be
tied to a known logic state.
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the
PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the
data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0
°
C to 70
°
C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
LFBGA GKE
Tape and reel
SN74SSTU32866GKER
SU866
Widebus+ is a trademark of Texas Instruments.
Copyright
2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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| SN74SSTU32866ZKER | 功能描述:緩沖器和線路驅(qū)動器 Single-Supply Voltage Translator RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74SSTUB32864ZKER | 功能描述:寄存器 25-Bit Configurable Registered Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SN74SSTUB32866ZKER | 功能描述:寄存器 25-B Con Reg Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SN74SSTUB32866ZWLR | 功能描述:寄存器 25B Configurable Registered Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SN74SSTV16857DGG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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