- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365664 > SN74LVTH652DB (Texas Instruments, Inc.) 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS PDF資料下載
參數(shù)資料
| 型號： | SN74LVTH652DB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| 中文描述： | 的3.3V ABT生根粉八路總線收發(fā)器和3冊態(tài)輸出 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 151K |
| 代理商： | SN74LVTH652DB |
SN54LVTH652, SN74LVTH652
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS706D – AUGUST 1997 – REVISED APRIL 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input; therefore,
when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
This device is fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH652 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LVTH652 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
CLKAB
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKBA
SAB
SBA
A1–A8
B1–B8
L
H
H or L
↑
↑
↑
H or L
↑
X
H or L
↑
H or L
↑
↑
↑
X
X
X
Input
Input
Isolation
L
H
X
X
Input
Input
Store A and B data
X
H
X
X
X
Input
Unspecified
Store A, hold B
H
H
X
Input
Output
Store A in both registers
L
X
X
X
X
Unspecified
Input
Hold A, store B
L
L
X
Output
Input
Store B in both registers
L
L
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54LVTH652 | Dual D-Type Flip-Flop with Set and Reset; Package: TSSOP-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2500 |
| SN54LVTH652FK | Dual D-Type Flip-Flop with Set and Reset; Package: SOEIAJ-14; No of Pins: 14; Container: Rail; Qty per Container: 50 |
| SN54LVTH652JT | Dual D-Type Flip-Flop with Set and Reset; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000 |
| SN54LVTH652W | Dual D-Type Flip-Flop with Set and Reset; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000 |
| SN74LVTH652DGV | 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVTH652DBR | 功能描述:總線收發(fā)器 Octal ABT RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVTH652DBRE4 | 功能描述:總線收發(fā)器 3.3V ABT Octal Bus Xcvr/Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVTH652DBRG4 | 功能描述:總線收發(fā)器 3.3V ABT Octal Bus Transceiver Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVTH652DGVR | 功能描述:總線收發(fā)器 Octal ABT RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVTH652DGVRE4 | 功能描述:總線收發(fā)器 Single-Supply Voltage Translator RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。