參數(shù)資料
型號(hào)： SN54LVTH652
廠商： Texas Instruments, Inc.
英文描述： Dual D-Type Flip-Flop with Set and Reset; Package: TSSOP-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2500
中文描述： 的3.3V ABT生根粉八路總線收發(fā)器和3冊(cè)態(tài)輸出
文件頁(yè)數(shù)： 1/10頁(yè)
文件大?。?/td> 151K
代理商： SN54LVTH652
SN54LVTH652, SN74LVTH652
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS706D – AUGUST 1997 – REVISED APRIL 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
I
off
and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), Ceramic Flat
(W) Package, and Ceramic (JT) DIPs
description
These bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V
CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
The ’LVTH652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB
and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
real-time and stored data. A low input selects real-time data and a high input selects stored data. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ’LVTH652 devices.
Copyright
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
SN54LVTH652 . . . JT OR W PACKAGE
SN74LVTH652 . . . DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
O
3 2 1
13 14
5
6
7
8
9
10
11
OEBA
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
4
15 16 17 18
A
G
N
B
B
B
S
C
N
SN54LVTH652 . . . FK PACKAGE
(TOP VIEW)
28 27 26
12
A
V
C
S
C
NC – No internal connection
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相關(guān)PDF資料
PDF描述
SN54LVTH652FK Dual D-Type Flip-Flop with Set and Reset; Package: SOEIAJ-14; No of Pins: 14; Container: Rail; Qty per Container: 50
SN54LVTH652JT Dual D-Type Flip-Flop with Set and Reset; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
SN54LVTH652W Dual D-Type Flip-Flop with Set and Reset; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
SN74LVTH652DGV 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74S08DR QUADRUPLE 2-INPUT POSITIVE-AND GATES
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