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參數(shù)資料
| 型號(hào)： | SN74LVT16615 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 17-Bit GTL/LVT Universal Bus Transceivers With 3-State Outputs(17位GTL/LVT通用總線收發(fā)器帶緩沖時(shí)鐘輸出) |
| 中文描述： | 17位的GTL /小型終端通用總線收發(fā)器與三態(tài)輸出（17位的GTL /小型終端通用總線收發(fā)器帶緩沖時(shí)鐘輸出） |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 187K |
| 代理商： | SN74LVT16615 |
SN74LVT16615
17-BIT GTL/LVT UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCBS264 – MARCH 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
14–1
Translates Between GTL Signal Levels and
LVCMOS, LVTTL, or 5-V TTL Signal Levels
Member of the Texas Instruments
Widebus
Family
Supports Mixed-Mode Signal Operation on
A Port (5-V Input and Output Voltages With
3.3-V V
CC
)
State-of-the-Art BiCMOS Design for
Low-Static Power Dissipation
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops With Qualified Storage Enable
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors on A Port
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Flow-Through Architecture Optimizes
PCB Layout
Packaged in Plastic 300-mil Shrink
Small-Outline and Thin Shrink
Small-Outline Packages
description
This 17-bit registered bus transceiver combines
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
It provides for a copy of CLKAB at GTL logic levels
(CLKOUT). It also provides a conversion of the
GTL clock to a TTL environment (CLKIN).
The B port operates at GTL levels while the A port and control pins are compatible with LVCMOS, LVTTL, or
5-V TTL logic levels.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock or latch-enable can be controlled by the chip-enable (CEAB
and CEBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low,
the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB is also low.
Output-enable OEAB is active-low. When OEAB is low, the outputs are active. When OEAB is high, the outputs
are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA,
and CEBA.
To ensure the high-impedance state during power-up or power-down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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OEAB
LEAB
A1
GND
A2
A3
3.3-V V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
3.3-V V
CC
A16
A17
GND
CLKIN
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
5-V V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
CLKOUT
CLKBA
CEBA
DGG OR DL PACKAGE
(TOP VIEW)
Widebus and UBT are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVT16646DGGR | 功能描述:總線收發(fā)器 3.3V ABT 16-Bit Bus Xcvr/Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVT16646DL | 功能描述:總線收發(fā)器 3.3V ABT 16-Bit Bus Xcvr/Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVT16646DLR | 功能描述:總線收發(fā)器 3.3V ABT 16-Bit Bus Xcvr/Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVT16835DGGR | 功能描述:總線收發(fā)器 Replaced by SN74LVTH16835DGGR RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVT16835DL | 功能描述:總線收發(fā)器 Replaced by SN74LVTH16835DL RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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