參數(shù)資料
型號(hào)： SN74LVCH16260
廠商： Texas Instruments, Inc.
英文描述： 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH(12-24多重D鎖存器(三態(tài)輸出))
中文描述： 12位至24位復(fù)用D型鎖存器（12-24多重?鎖存器（三態(tài)輸出））
文件頁(yè)數(shù)： 1/9頁(yè)
文件大?。?/td> 198K
代理商： SN74LVCH16260
SN74ALVCH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS570B – MARCH 1996 – REVISED NOVEMBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
B-Port Outputs Have Equivalent 26-
Series Resistors, So No External Resistors
Are Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates
the Need for External Pullup/Pulldown
Resistors
Package Options Include Thin-Shrink
Small-Outline (DGG) and Plastic Shrink
Small-Outline (DL) Packages
description
This 12-bit to 24-bit multiplexed D-type latch is
designed for 2.3-V to 3.6-V
CC
operation.
The SN74ALVCH162260 is used in applications
where two separate datapaths must be
multiplexed onto, or demultiplexed from, a
single datapath. Typical applications include
multiplexing and/or demultiplexing address and
data
information
in
bus-interface applications. This device is also
useful in memory-interleaving applications.
microprocessor
or
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The
output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B
control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The B outputs, which are designed to sink up to 12 mA, include 26-
resistors to reduce overshoot and
undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
DGG OR DL PACKAGE
(TOP VIEW)
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OEA
LE1B
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
LE2B
SEL
OE2B
LEA2B
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
LEA1B
OE1B
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1996, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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