參數(shù)資料
型號： SN74LVCH16544
廠商： Texas Instruments, Inc.
英文描述： 16-Bit Registered Transceivers(16位記錄收發(fā)器(三態(tài)輸出))
中文描述： 16位注冊收發(fā)器（16位記錄收發(fā)器（三態(tài)輸出））
文件頁數(shù)： 1/6頁
文件大小： 133K
代理商： SN74LVCH16544
SN74LVC16544
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS351 – MARCH 1994
Copyright
1994, Texas Instruments Incorporated
8–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit registered transceiver is designed for
low-voltage (3.3 V) V
CC
operation.
The SN74LVC16544 can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate
latch-enable (LEAB or LEBA) and output-enable
(OEAB or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
The A-to-B enable (CEAB) input must be low in
order to enter data from A or to output data from
B. If CEAB is low and LEAB is low, the A-to-B
latches are transparent; a subsequent low-to-high
transition of LEAB puts the A latches in the storage
mode. With CEAB and OEAB both low, the 3-state
B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar
but requires using the CEBA, LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16544 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
B
CEAB
H
LEAB
X
OEAB
X
A
X
Z
L
X
H
X
Z
L
H
L
X
B0
H
L
L
L
L
L
L
L
H
L
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
Output level before the indicated steady-state input
conditions were established.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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