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參數(shù)資料
| 型號(hào)： | SN74GTLPH16912VR |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | CAP |
| 中文描述： | 18位LVTTL至GTLP通用總線收發(fā)器 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 218K |
| 代理商： | SN74GTLPH16912VR |
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C
–
OCTOBER 1999
–
REVISED JULY 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Notes 4 through 7)
MIN
NOM
MAX
UNIT
VCC,
BIAS VCC
Supply voltage
3.15
3.3
3.45
V
VTT
Termination voltage
GTL
1.14
1.2
1.26
V
GTLP
1.35
1.5
1.65
VREF
Reference voltage
GTL
0.74
0.8
0.87
V
GTLP
0.87
1
1.1
VI
Input voltage
B port
VTT
5.5
V
Except B port
VCC
VIH
High level input voltage
High-level input voltage
B port
VREF+0.05
V
Except B port
2
VIL
Low level input voltage
Low-level input voltage
B port
VREF
–
0.05
0.8
V
Except B port
IIK
IOH
Input clamp current
–
18
mA
High-level output current
A port
–
24
mA
IOL
Low level output current
Low-level output current
A port
24
mA
B port
50
t/
v
t/
VCC
TA
NOTES:
Input transition rise or fall rate
Outputs enabled
10
ns/V
μ
s/V
°
C
Power-up ramp rate
20
Operating free-air temperature
–
40
85
4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF
inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any
connection sequence is acceptable, but generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances
if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT
>
0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
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| SN74GTLPH16916GR | 功能描述:特定功能邏輯 17-Bit LVTTL-to-GTLP Univ Bus Trnscvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74GTLPH16916VR | 功能描述:特定功能邏輯 17-Bit LVTTL-to-GTLP Univ Bus Trnscvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74GTLPH16927GR | 功能描述:特定功能邏輯 18-Bit LVTTL-to-GTLP Bus Trnscvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74GTLPH16927KR | 功能描述:總線收發(fā)器 18-Bit LVTTL-to-GTLP Bus Trnscvr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74GTLPH16927VR | 功能描述:特定功能邏輯 18-Bit LVTTL-to-GTLP Bus Trnscvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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