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參數(shù)資料
| 型號： | SN74GTLPH16912VR |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | CAP |
| 中文描述： | 18位LVTTL至GTLP通用總線收發(fā)器 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 218K |
| 代理商： | SN74GTLPH16912VR |
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C
–
OCTOBER 1999
–
REVISED JULY 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–
40
°
C to 85
°
C
TSSOP
–
DGG
Tape and reel
SN74GTLPH16912GR
GTLPH16912
TVSOP
–
DGV
Tape and reel
SN74GTLPH16912VR
GL912
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74GTLPH16916GR | 功能描述:特定功能邏輯 17-Bit LVTTL-to-GTLP Univ Bus Trnscvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74GTLPH16916VR | 功能描述:特定功能邏輯 17-Bit LVTTL-to-GTLP Univ Bus Trnscvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74GTLPH16927GR | 功能描述:特定功能邏輯 18-Bit LVTTL-to-GTLP Bus Trnscvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74GTLPH16927KR | 功能描述:總線收發(fā)器 18-Bit LVTTL-to-GTLP Bus Trnscvr RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74GTLPH16927VR | 功能描述:特定功能邏輯 18-Bit LVTTL-to-GTLP Bus Trnscvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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