參數(shù)資料
型號: SN74GTL16612DGG
廠商: Texas Instruments, Inc.
英文描述: 18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS
中文描述: 18位LVTTL-TO-GTL/GTL通用總線收發(fā)器
文件頁數(shù): 4/13頁
文件大小: 193K
代理商: SN74GTL16612DGG
www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Recommended Operating Conditions
(1)(2)(3)(4)
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K–JUNE 1994–REVISED JULY 2005
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.6
UNIT
3.3 V
5 V
A-port and control inputs
B port and V
REF
A port
B port
A port
B port
V
CC
Supply voltage range
V
7
7
V
I
Input voltage range
(2)
V
4.6
7
V
O
Voltage range applied to any output in the high or power-off state
(2)
V
4.6
128
80
64
±
100
–50
–50
64
56
150
I
O
Current into any output in the low state
mA
I
O
Current into any A-port output in the high state
(3)
Continuous current through each V
CC
or GND
Input clamp current
Output clamp current
mA
mA
mA
mA
I
IK
I
OK
V
I
< 0
V
O
< 0
DGG package
DL package
θ
JA
Package thermal impedance
(4)
°
C/W
T
stg
Storage temperature range
–65
°
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and V
> V
.
The package thermal impedance is calculated in accordance with JESD 51-7.
(2)
(3)
(4)
SN54GTL16612
MIN
NOM
3.15
4.75
1.14
1.35
0.74
0.87
SN74GTL16612
MIN
NOM
3.15
4.75
1.14
1.35
0.74
0.87
UNIT
MAX
3.45
5.25
1.26
1.65
0.87
1.1
V
TT
5.5
MAX
3.45
5.25
1.26
1.65
0.87
1.1
V
TT
5.5
3.3 V
5 V
GTL
GTL+
GTL
GTL+
B port
Except B port
B port
Except B port
B port
Except B port
3.3
3.3
V
CC
Supply voltage
V
5
5
1.2
1.5
0.8
1.2
1.5
0.8
Termination
voltage
V
TT
V
V
REF
Reference voltage
V
1
1
V
I
Input voltage
V
V
REF
+ 50 mV
V
REF
+ 50 mV
High-level
input voltage
V
IH
V
2
2
V
REF
– 50 mV
V
REF
– 50 mV
Low-level
input voltage
V
IL
V
0.8
–18
0.8
–18
I
IK
Input clamp current
High-level
output current
mA
I
OH
A port
–32
–32
mA
A port
B port
64
40
64
40
85
Low-level
output current
I
OL
mA
T
A
Operating free-air temperature
–55
125
–40
°
C
(1)
All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Normal connection sequence is GND first, V
= 5 V second, and V
= 3.3 V, I/O, control inputs, V
and V
(any order) last.
V
TT
and R
can be adjusted to accommodate backplane impedances if the dc recommended I
OL
ratings are not exceeded.
V
REF
can be adjusted to optimize noise margins, but normally is two-thirds V
TT
.
(2)
(3)
(4)
4
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