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參數(shù)資料
| 型號(hào)： | SN74GTL16612DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS |
| 中文描述： | 18位LVTTL-TO-GTL/GTL通用總線收發(fā)器 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 193K |
| 代理商： | SN74GTL16612DGG |
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs.
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A
data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs
are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that
for A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K–JUNE 1994–REVISED JULY 2005
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
SN74GTL16612DL
SN74GTL16612DLR
SN74GTL16612DGGR
SNJ54GTL16612WD
TOP-SIDE MARKING
Tube
Tape and reel
Tape and reel
Tube
SSOP – DL
GTL16612
–40
°
C to 85
°
C
TSSOP – DGG
CFP – WD
GTL16612
SNJ54GTL16612WD
–55
°
C to 125
°
C
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(1)
INPUTS
LEAB
X
L
L
H
H
L
L
L
OUTPUT
B
MODE
CEAB
X
L
L
X
X
L
L
H
OEAB
H
L
L
L
L
L
L
L
CLKAB
X
H
L
X
X
↑
↑
X
A
X
X
X
L
H
L
H
X
Z
Isolation
B
0(2)
B
0(3)
L
H
L
H
B
0(3)
Latched storage of A data
Transparent
Clocked storage of A data
Clock inhibit
(1)
(2)
(3)
A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA.
Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low
Output level before the indicated steady-state input conditions were established
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74GTL16612DGGR | 功能描述:轉(zhuǎn)換 - 電壓電平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTL16612DL | 功能描述:轉(zhuǎn)換 - 電壓電平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTL16612DLG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTL16612DLR | 功能描述:轉(zhuǎn)換 - 電壓電平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTL16612DLRG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 3-8-Line Decoder Demltplxr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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