參數(shù)資料
型號: SN74FB2042
廠商: Texas Instruments, Inc.
英文描述: 8-Bit TTL/BTL Transceivers(8位TTL/BTL收發(fā)器)
中文描述: 8位的TTL /橋接收發(fā)器(8位的TTL /橋接收發(fā)器)
文件頁數(shù): 1/7頁
文件大?。?/td> 149K
代理商: SN74FB2042
SN74FB2042
8-BIT TTL/BTL TRANSCEIVER
SCBS483 – NOVEMBER 1991 – REVISED JANUARY 1994
BIAS V
CC
Pin Minimizes Signal Distortion
During Live Insertion/Withdrawal
Packaged in Plastic Quad-Flat Packages
(RC) With 0.65-mm Pin Pitches
B-Port Biasing Network Preconditions the
Connector and PC Trace to the Backplane
Transceiver Logic High-Level Voltage
Copyright
1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Compatible With IEEE 1194.1-1991 (BTL)
and IEEE 896.2-1991 (Futurebus+)
Standards
TTL A Port, Backplane Transceiver Logic
B Port
Open-Collector B-Port Outputs Sink 100 mA
Minimum B-Port Edge Rate = 2 ns
Isolated Logic-Ground and Bus-Ground
Pins Reduce Noise
A
A
A
O
T
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
G
A
A
B
A
T
A
G
B
A
G
B
V
C
V
C
RC PACKAGE
(TOP VIEW)
B
C
T
GND
AI2
AI3
AO3
GND
AO4
GND
AI4
AI5
AO5
GND
AO6
GND
GND
B2
GND
B3
GND
B4
GND
B5
GND
B6
GND
B7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
B
C
O
V
C
O
T
description
The SN74FB2042 is an 8-bit transceiver designed to translate signals between TTL and backplane transceiver
logic (BTL) environments. It is specifically designed to be compatible with IEEE 1194.1-1991 (BTL) and
IEEE 896.2-1991 (Futurebus+) standards.
The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA and have
minimum output edge rates of 2 ns. Two output enables, OEB and OEB, are provided for the B outputs. When
OEB is high and OEB is low, the B port is active and reflects the data present at the A-input pins. When OEB
is low, OEB is high, or V
CC
is typically less than 2.5 V, the B port is turned off.
The A port operates at TTL-signal levels and has split input and output pins. The A outputs reflect the data at
the B port when the A-port output enable, OEA, is high. When OEA is low or when V
CC
is typically less than 2.5 V,
the A outputs are in the high-impedance state.
Pins are allocated for the four-wire IEEE 1149.1 (JTAG) test bus, which will be implemented in a future version
of the SN74FB2042. Currently TMS and TCK are not connected and TDI is shorted to TDO.
fb2042–1
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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