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參數(shù)資料
| 型號(hào)： | SN74AVC2T45YEPR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS |
| 中文描述： | 雙位雙電源總線收發(fā)器可配置電壓轉(zhuǎn)換和3態(tài)輸出 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 376K |
| 代理商： | SN74AVC2T45YEPR |
www.ti.com
APPLICATION INFORMATION
V
CC1
V
CC1
V
CC2
SYSTEM-1
SYSTEM-2
1
2
3
4
8
7
6
5
DIR CTRL
I/O-1
Pullup/Pulldown
or Bus Hold
(1)
V
CC2
I/O-2
Pullup/Pulldown
or Bus Hold
(1)
Enable Times
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES531F–DECEMBER 2003–REVISED MAY 2005
Figure 13
shows the SN74AVC2T45 used in a bidirectional logic level-shifting application. Since the
SN74AVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from
SYSTEM-2 to SYSTEM-1.
STATE
1
DIR CTRL
H
I/O-1
Out
I/O-2
In
DESCRIPTION
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are
disabled.
The bus-line state depends on pullup or pulldown.
(1)
DIR bit is flipped. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on pullup or pulldown.
(1)
SYSTEM-2 data to SYSTEM-1
2
H
Hi-Z
Hi-Z
3
L
Hi-Z
Hi-Z
4
L
Out
In
(1)
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 13. Bidirectional Logic Level-Shifting Application
Calculate the enable times for the SN74AVC2T45 using the following formulas:
t
PZH
(DIR to A) = t
PLZ
(DIR to B) + t
PLH
(B to A)
t
PZL
(DIR to A) = t
PHZ
(DIR to B) + t
PHL
(B to A)
t
PZH
(DIR to B) = t
PLZ
(DIR to A) + t
PLH
(A to B)
t
PZL
(DIR to B) = t
PHZ
(DIR to A) + t
PHL
(A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVC2T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
15
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| SN74AVC2T45YZTR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| SN74AVC2T872YFPR | 功能描述:轉(zhuǎn)換 - 電壓電平 Vltg-Level Shifter for IC-USB Interface RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74AVC32T245GKER | 功能描述:轉(zhuǎn)換 - 電壓電平 Stereo Low Pwr Voice Band Codec RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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