參數(shù)資料
型號: SN74AVC16831DBBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: AVC SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO80
封裝: TVSOP-80
文件頁數(shù): 1/11頁
文件大?。?/td> 565K
代理商: SN74AVC16831DBBR
SN74AVC16831
9-BIT 1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES179F – DECEMBER 1998 – REVISED FEBRUARY 2000
2–205
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D Ioff Supports Partial-Power-Down Mode
Operation
D Packaged in Thin Very Small-Outline
Package
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC
)
Circuitry Technology and Applications, literature number SCEA009.
136
–128
–144
–160
0.4
0.8
1.2
1.6
2.0
2.4
2.8
170
153
119
102
85
68
51
34
17
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
TA = 25°C
Process = Nominal
IOL – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
Output
V
oltage
V
OL
V
TA = 25°C
Process = Nominal
IOH – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
Output
V
oltage
V
OH
V
–80
–96
–112
–32
–48
–64
0
–16
Figure 1. Output Voltage vs Output Current
This 9-bit 1-to-4 address register/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for
1.65-V to 3.6-V VCC operation.
The device is ideal for use in applications in which a single address bus is driving four separate memory
locations. The SN74AVC16831 can be used as a buffer or a register, depending on the logic level of the select
(SEL) input.
When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by
the two output-enable (OE) controls. Each OE controls two groups of nine outputs.
When SEL is logic low, the device is in the register mode. The register is an edge-triggered D-type flip-flop. On
the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers. OE
controls operate the same as in buffer mode.
PRODUCT
PREVIEW
Copyright
2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
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