參數(shù)資料
型號: SN74AVC126DR
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: AVC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝: PLASTIC, MS-012AB, SOIC-14
文件頁數(shù): 1/13頁
文件大?。?/td> 217K
代理商: SN74AVC126DR
www.ti.com
PRODUCT
PREVIEW
FEATURES
DESCRIPTION
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
153
136
119
102
85
68
51
34
17
TA = 25°C
Process = Nominal
IOL - Output Current - mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
-Output
V
oltage
-
V
OL
V
2.8
2.4
2.0
1.6
1.2
0.8
0.4
-32
-48
-64
-80
-96
-112
-128
-144
-16
TA = 25°C
Process = Nominal
IOH - Output Current - mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
-Output
V
oltage
-
V
OH
V
170
0
-160
SN74AVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES255B – APRIL 1999 – REVISED DECEMBER 2005
EPIC (Enhanced-Performance Implanted
Overvoltage-Tolerant Inputs/Outputs Allow
CMOS) Submicron Process
Mixed-Voltage-Mode Data Communications
DOC (Dynamic Output Control) Circuit
I
off Supports Partial-Power-Down Mode
Dynamically Changes Output Impedance,
Operation
Resulting in Noise Reduction Without Speed
Package Options Include Plastic
Degradation
Small-Outline (D), Thin Very Small-Outline
Dynamic Drive Capability Is Equivalent to
(DGV), and Thin Shrink Small-Outline (PW)
Standard Outputs With I
OH and IOL of ±24 mA
Packages
at 2.5-V V
CC
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC) Circuitry
Technology and Applications, literature number SCEA009.
Figure 1. Output Voltage vs Output Current
This quadruple bus buffer gate is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
The SN74AVC126 features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC126 is characterized for operation from –40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC, DOC are trademarks of Texas Instruments.
PRODUCT PREVIEW information concerns products in the
Copyright 1999–2005, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
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