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參數(shù)資料
| 型號： | SN74AUC2G125YEPR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS |
| 中文描述： | 雙總線緩沖門具有三態(tài)輸出 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 259K |
| 代理商： | SN74AUC2G125YEPR |
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
CC
/2
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
2
×
V
CC
Open
GND
R
L
R
L
Data Input
Timing Input
V
CC
0 V
V
CC
0 V
0 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
V
CC
0 V
Input
Output
Waveform 1
S1 at 2
×
V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CC
0 V
V
OL
+ V
V
OH
V
≈
0 V
V
CC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
2
×
V
CC
GND
TEST
S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, Z
O
= 50
, slew rate
≥
1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
V
CC
/2
V
CC
/2
0.8 V
1.2 V
±
0.1 V
1.5 V
±
0.1 V
1.8 V
±
0.15 V
2.5 V
±
0.2 V
1.8 V
±
0.15 V
2.5 V
±
0.2 V
2 k
2 k
2 k
2 k
2 k
1 k
500
V
CC
R
L
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
V
C
L
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
SN74AUC2G02
DUAL 2-INPUT POSITIVE-NOR GATE
SCES441A–MAY 2003–REVISED MARCH 2005
Figure 1. Load Circuit and Voltage Waveforms
5
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