參數(shù)資料
型號(hào): SN74AUC2G125YEPR
廠商: Texas Instruments, Inc.
英文描述: DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
中文描述: 雙總線緩沖門(mén)具有三態(tài)輸出
文件頁(yè)數(shù): 2/11頁(yè)
文件大?。?/td> 259K
代理商: SN74AUC2G125YEPR
www.ti.com
1A
1B
1Y
1
2
7
2A
2B
2Y
5
6
3
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
SN74AUC2G02
DUAL 2-INPUT POSITIVE-NOR GATE
SCES441A–MAY 2003–REVISED MARCH 2005
FUNCTION TABLE
(EACH GATE)
INPUTS
OUTPUT
Y
A
H
X
L
B
X
H
L
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
3.6
3.6
3.6
UNIT
V
V
V
V
mA
mA
mA
mA
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage range
(2)
Voltage range applied to any output in the high-impedance or power-off state
(2)
Output voltage range
(2)
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CC
or GND
V
CC
+ 0.5
V
I
< 0
V
O
< 0
–50
–50
±
20
±
100
220
227
102
150
DCT package
DCU package
YEP/YZP package
θ
JA
Package thermal impedance
(3)
°
C/W
T
stg
Storage temperature range
–65
°
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
(2)
(3)
2
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