參數(shù)資料
型號: SN74AUC16374GQLR
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
中文描述: 16位邊沿觸發(fā)的D -型觸發(fā)器具有三態(tài)輸出
文件頁數(shù): 1/12頁
文件大?。?/td> 299K
代理商: SN74AUC16374GQLR
www.ti.com
FEATURES
Member of the Texas Instruments Widebus
Family
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
I
off
Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max t
pd
of 2 ns at 1.8 V
Low Power Consumption, 20-
μ
A Max I
CC
±
8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This
16-bit
edge-triggered
operational at 0.8-V to 2.7-V V
CC
, but is designed
specifically for 1.65-V to 1.95-V V
CC
operation.
The
SN74AUC16374
is
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. It can be used as
two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CLK) input, the Q
outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403D–JULY 2002–REVISED JUNE 2005
D-type
flip-flop
is
particularly
suitable
for
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
SN74AUC16374DGGR
SN74AUC16374DGVR
SN74AUC16374GQLR
TOP-SIDE MARKING
AUC16374
MH374
MH374
TSSOP – DGG
TVSOP – DGV
VFBGA – GQL
(2)
Tape and reel
Tape and reel
Tape and reel
–40°C to 85°C
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Package preview
(2)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2002–2005, Texas Instruments Incorporated
相關(guān)PDF資料
PDF描述
SN74AUC16374ZQLR 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC16501 Analog Multiplexer/Demultiplexer; Package: SOEIAJ-16; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2000
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SN74AUC17RGYR 功能描述:緩沖器和線路驅(qū)動器 Hex Schmitt-Trigger Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
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