參數資料
型號: SN74AUC16501
廠商: Texas Instruments, Inc.
英文描述: Analog Multiplexer/Demultiplexer; Package: SOEIAJ-16; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2000
中文描述: 18位通用總線收發(fā)器和三態(tài)輸出
文件頁數: 1/13頁
文件大?。?/td> 236K
代理商: SN74AUC16501
www.ti.com
FEATURES
Member of the Texas Instruments Widebus
Family
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
I
off
Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max t
pd
of 2 ns at 1.8 V
Low Power Consumption, 10
μ
A at 1.8 V
±
8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 18-bit universal bus transceiver is operational at
0.8-V to 2.7-V V
CC
, but is designed specifically for
1.65-V to 1.95-V V
CC
operation.
Data
flow
in
each
direction
output-enable
(OEAB
and
(LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in
the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A data is
stored
in
the
latch/flip-flop
transition of CLKAB. When OEAB is high, the outputs
are active. When OEAB is low, the outputs are in the
high-impedance state.
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES418–DECEMBER 2002–REVISED JUNE 2005
is
controlled
latch-enable
by
OEBA),
on
the
low-to-high
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
SN74AUC16501DGGR
SN74AUC16501DGVR
SN74AUC16501GQLR
TOP-SIDE MARKING
AUC16501
MH501
MH501
TSSOP – DGG
TVSOP – DGV
VFBGA – GQL
Tape and reel
Tape and reel
Tape and reel
–40°C to 85°C
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2002–2005, Texas Instruments Incorporated
相關PDF資料
PDF描述
SN74AUC16501DGVR Quad 2-Input XOR Gate; Package: TSSOP-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2500
SN74AUC16501DGG Analog Multiplexer/Demultiplexer; Package: SOEIAJ-16; No of Pins: 16; Container: Rail; Qty per Container: 50
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SN74AUC16501DGV 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AUC16501GQLR 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
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