- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373472 > SN74ALVCH16903DLR (Texas Instruments, Inc.) 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS PDF資料下載
參數(shù)資料
| 型號： | SN74ALVCH16903DLR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS |
| 中文描述： | 3.3 V的12位通用總線驅(qū)動器，帶有奇偶校驗器和雙三態(tài)輸出 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 213K |
| 代理商： | SN74ALVCH16903DLR |
www.ti.com
FEATURES
Member of the Texas Instruments Widebus
Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
Checks Parity
Able to Cascade With a Second
SN74ALVCH16903
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
DESCRIPTION
This 12-bit universal bus driver is designed for 2.3-V
to 3.6-V V
CC
operation.
The SN74ALVCH16903 has dual outputs and can
operate as a buffer or an edge-triggered register. In
both modes, parity is checked on APAR, which
arrives one cycle after the data to which it applies.
The YERR output, which is produced one cycle after
APAR, is open drain.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OE
1Y1
1Y2
GND
2Y1
2Y2
V
CC
3Y1
3Y2
4Y1
GND
4Y2
5Y1
5Y2
6Y1
6Y2
7Y1
GND
7Y2
8Y1
8Y2
V
CC
9Y1
9Y2
GND
10Y1
10Y2
PAROE
CLK
1A
11A/YERREN
GND
11Y1
11Y2
V
CC
2A
3A
4A
GND
12A
12Y1
12Y2
5A
6A
7A
GND
APAR
8A
YERR
V
CC
9A
MODE
GND
10A
PARI/O
CLKEN
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
SCES095D–MARCH 1997–REVISED SEPTEMBER 2004
MODE selects one of the two data paths. When
MODE
is
low,
the
device
edge-triggered register. On the positive transition of
the clock (CLK) input and when the clock-enable
(CLKEN) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of
CLK and when CLKEN is high, only data set up at the 9A–12A inputs is stored in their internal registers. When
MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs.
11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked into
the YERR output register.
operates
as
an
When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output
(PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and
PAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When used
in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903.
A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state
(high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operation of the device. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 1997–2004, Texas Instruments Incorporated
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ALVCH16973DLR | 8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH FOUR INDEPENDENT BUFFERS |
| SN74ALVCH244NSR | OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| SN74ALVCH244NSRE4 | OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| SN74ALVCH244NSRG4 | OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| SN74ALVCH373GQNR | OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ALVCH16952DGG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| SN74ALVCH16952DGGR | 功能描述:總線收發(fā)器 16bit Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVCH16952DGVR | 功能描述:總線收發(fā)器 16bit Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVCH16952DL | 功能描述:總線收發(fā)器 16bit Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVCH16952DLR | 功能描述:總線收發(fā)器 16bit Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。