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參數(shù)資料
| 型號(hào)： | SN74ABT32373 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 32-Bit Transceivers With D-Type Latches And 3-State Outputs(32位收發(fā)器帶D鎖存器(三態(tài)輸出)) |
| 中文描述： | 32位收發(fā)器使用D型鎖存器和三態(tài)輸出（32位收發(fā)器帶?鎖存器（三態(tài)輸出）） |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 126K |
| 代理商： | SN74ABT32373 |
SN54ABT32373, SN74ABT32373
32-BIT TRANSCEIVERS WITH D-TYPE LATCHES
AND 3-STATE OUTPUTS
SCBS460 – JUNE 1992–REVISED OCTOBER 1992
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 5 V, T
A
= 25
°
C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
High-Drive Outputs (–32-mA I
OH
,
64-mA I
OL
)
Bus-Hold Inputs Eliminate the Need for
External Pullup Resistors
Packaged in 100-Pin Plastic Shrink Quad
Flat Pack (SQFP) With 14
×
14-mm Package
Body Using 0.5-mm Lead Pitch
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1992, Texas Instruments Incorporated
1
Members of the Texas Instruments
Widebus+
Family
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
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SN74ABT32373 . . . PZ PACKAGE
(TOP VIEW)
1A7
1A8
GND
2A1
2A2
2A3
2A4
GND
2A5
2A6
2A7
2A8
VCC
3A1
3A2
3A3
3A4
GND
3A5
3A6
3A7
3A8
GND
4A1
4A2
1B7
1B8
GND
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
2B8
V
CC
3B1
3B2
3B3
3B4
GND
3B5
3B6
3B7
3B8
GND
4B1
4B2
1
1
1
V
C
G
4
4
4
4
1
1
1
G
1
1
2
2
2
2
1
1
G
1
1
1
G
1
1
1
G
4
4
4
4
G
3
3
3
3
4
4
4
4
G
G
4
4
4
4
V
C
50
1
2
3
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Widebus+ and EPIC-
ΙΙ
B are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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