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參數(shù)資料
| 型號： | SN65LVDS302_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER |
| 中文描述： | 可編程27位串行到并行接收機 |
| 文件頁數(shù)： | 1/41頁 |
| 文件大?。?/td> | 1412K |
| 代理商： | SN65LVDS302_07 |
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www.ti.com
FEATURES
Serial Interface Technology
Compatible with FlatLink3G such as
SN65LVDS301
Supports Video Interfaces up to 24-bit RGB
Data and 3 Control Bits Received over 1, 2 or
3 SubLVDS Differential Lines
SubLVDS Differential Voltage Levels
Up to 1.755 Gbps Data Throughput
Three Operating Modes to Conserve Power
–
Active mode QVGA - 17 mW
–
Typical Shutdown - 0.7
μ
W
–
Typical Standby Mode - 27
μ
W Typical
Bus-Swap Function for PCB-Layout Flexibility
ESD Rating > 4 kV (HBM)
Pixel Clock Range of 4 MHz–65 MHz
Failsafe on all CMOS Inputs
Packaged in 5 mm x 5 mm MicroStar Junior
μ
BGA
with 0,5 mm Ball Pitch
Very low EMI meets SAE J1752/3 'Kh'-spec
APPLICATIONS
Small Low-Emission Interface between
Graphics Controller and LCD Display
Mobile Phones & Smart Phones
Portable Multimedia Players
DESCRIPTION
The
SN65LVDS302
FlatLink3G compliant serial input data to 27
parallel data outputs. The SN65LVDS302 receiver
contains one shift register to load 30 bits from 1, 2 or
3 serial inputs and latches the 24 pixel bits and 3
control bits out to the parallel CMOS outputs after
checking the parity bit. If the parity check confirms
correct parity, the Channel Parity Error (CPE) output
remains low. If a parity error is detected, the CPE
output generates a high pulse while the data output
bus disregards the newly-received pixel. Instead, the
last data word is held on the output bus for another
clock cycle.
Flatlink 3G
1
4
7
*
3
6
9
#
2
5
8
0
Application
Processor
with
RGB
Video
Interface
LVDS302
LVDS301
LCD
Driver
DATA
CLK
SN65LVDS302
SLLS733B–JUNE 2006–REVISED FEBRUARY 2007
PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
The serial data and clock are received via Sub
Low-Voltage Differential Signalling (SubLVDS) lines.
The SN65LVDS302 supports three operating power
modes (Shutdown, Standby, and Active) to conserve
power.
When receiving, the PLL locks to the incoming clock
CLK and generates an internal high-speed clock at
the line rate of the data lines. The data is serially
loaded
into
a
shift
register
high-speed clock. The deserialized data is presented
on the parallel output bus with a recreation of the
Pixel
clock
PCLK
generated
high-speed clock. If no input CLK signal is present,
the output bus is held static with the PCLK and DE
held low, while all other parallel outputs are pulled
high.
using
the
internal
from
the
internal
The parallel (CMOS) output bus offers a bus-swap
feature. The SWAP control pin controls the output
pin order of the output pixel data to be either R[7:0].
G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7],
VS, HS, DE. This gives a PCB designer the flexibility
to better match the bus to the LCD driver pinout or to
put the receiver device on the top side or the bottom
side of the PCB. The F/S control input selects
between a slow CMOS bus output rise time for best
EMI and power consumption and a fast CMOS
output for increased speed or higher load designs.
receiver
de-serializes
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
μ
BGA is a registered trademark of Tessera, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2006–2007, Texas Instruments Incorporated
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN65LVDS302ZQE | 功能描述:串行器/解串器 - Serdes Program 27B Display Ser Interface RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SN65LVDS302ZQER | 功能描述:串行器/解串器 - Serdes Programmable 27B Displ Ser Interface RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SN65LVDS303ZQE | 功能描述:IC PROG 27BIT SERDES TX 80-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:65LVDS 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| SN65LVDS303ZQER | 功能描述:串行器/解串器 - Serdes QVGA-VGA 27B Display Serial Interface RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SN65LVDS304ZQER | 功能描述:串行器/解串器 - Serdes QVGAVGA 27B Display Ser Interface RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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