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參數(shù)資料
| 型號(hào)： | SN65LVDS047PWG4 |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LVDS QUAD DIFF DVR 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | 65LVDS |
| 類(lèi)型： | 線路驅(qū)動(dòng)器，發(fā)射器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/0 |
| 規(guī)程： | LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
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SWITCHING CHARACTERISTICS
SLLS416B – JUNE 2000 – REVISED DECEMBER 2003
over recommended operating conditions (see (1), (2) and (3) )(unless otherwise noted)
TYP(
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
4)
tPHL
Differential propagation delay, high-to-low
1.4
1.8
2.8
ns
tPLH
Differential propagation delay, low-to-high
1.4
1.8
2.8
ns
tSK(p)
Differential pulse skew (tPHLD - tPLHD), see (5)
50
300
ps
tSK(o)
Channel-to-channel skew, see (6)
40
300
ps
RL = 100 ,, CL = 15 pF,
tSK(pp)
Differential part-to-part skew, see (7)
1
ns
tSK(lim)
Differential part-to-part skew, see (8)
1.2
ns
tr
Rise time
0.5
1.5
ns
tf
Fall time
0.5
1.5
ns
tPHZ
Disable time high to Z
5.5
8
ns
tPLZ
Disable time low to Z
5.5
8
ns
RL = 100 ,, CL = 15 pF,
tPZH
Enable time Z to high
8.5
12
ns
tPZL
Enable time Z to low
8.5
12
ns
f(MAX)
Maximum operating frequency, see (9)
250
MHz
(1)
Generator waveform for all tests unless otherwise: f = 1 MHz, Zo = 50 , tr < 1 ns, and tf < 1 ns.
(2)
CL includes probe and jig capacitance.
(3)
All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
(4)
All typical values are given for: VCC = 3.3 V, TA = 25°C.
(5)
tSK(p)|tPHL-tPLH| is the magnitude difference in differential propagation delay time between the positive going edge andthe negative going
edge of the same channel.
(6)
tSK(o) is the differential channel-to-channel skew of any event on the same device.
(7)
tSK(pp) is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified differential
propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature
range.
(8)
tSK(lim) part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSK(lim) is defined as|Min - Max|
differential propagation delay.
(9)
f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to55,VOD >
250 mV, all channels switching
4
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| SN65LVDS048ADR | 功能描述:LVDS 接口集成電路 Quad LVDS Receiver w/Flow-Thru Pinout RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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