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參數(shù)資料
| 型號： | SN55LVDS32FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-SPEED DIFFERENTIAL LINE RECEIVERS |
| 中文描述： | 高速差分線路接收器 |
| 文件頁數(shù)： | 7/37頁 |
| 文件大?。?/td> | 916K |
| 代理商： | SN55LVDS32FK |
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SLLS262N JULY 1997 REVISED MARCH 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN65LVDSxxxx electrical characteristics over recommended operating conditions (unless
otherwise noted)
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VOH
High-level output voltage
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Supply current
PARAMETER
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Disabled
TEST CONDITIONS
0.25
SN65LVDS9637
TYP
MAX
UNIT
MIN
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10
5.5
Input current (A or B inputs)
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10
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VOH
High-level output voltage
Enabled,
18
0.5
10
V
V
SN65LVDS9637
No load
2
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The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going
differential input voltage threshold only.
Low-level input current (EN, G, or G inputs)
High-impedance output current
°
C and with VCC = 3.3 V.
No load
mA
20
VI = 0
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mA
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μ
A
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μ
A
μ
A
±
10
SN65LVDSxxxx switching characteristics over recommended operating conditions (unless
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tf
Output signal fall time, 80% to 20%
tPHZ
Propagation delay time, high-level-to-high-impedance output
tPLZ
Propagation delay time, low-level-to-high-impedance output
direction while driving identical specified loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, same temperature, and have identical packages and test circuits.
PARAMETER
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TEST CONDITIONS
SN65LVDS9637
MAX
3
UNIT
tPLH
Propagation delay time, low-to-high-level output
Output signal rise time, 20% to 80%
MIN
1.5
TYP
2.1
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ns
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Channel-to-channel output skew§
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0.4
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0.6
0.7
6.5
5.5
ns
12
ns
12
ns
12
ns
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