參數(shù)資料
型號(hào)： SN54LVTH182512
廠商： Texas Instruments, Inc.
英文描述： 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT掃描測(cè)試裝置(18位通用總線收發(fā)器))
中文描述： 的3.3V ABT生根粉掃描測(cè)試設(shè)備與18位通用總線收發(fā)器（3.3VABT掃描測(cè)試裝置（18位通用總線收發(fā)器））
文件頁數(shù)： 1/34頁
文件大?。?/td> 726K
代理商： SN54LVTH182512
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS671A – AUGUST 1996 – REVISED JUNE 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
SCOPE
Family of Testability Products
Members of the Texas Instruments
Widebus
Family
State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
B-Port Outputs of ’LVTH182512 Devices
Have Equivalent 25-
Series Resistors, So
No External Resistors Are Required
Compatible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
SCOPE
Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
Package Options Include 64-Pin Plastic
Thin Shrink Small Outline (DGG) and 64-Pin
Ceramic Dual Flat (HKC) Packages Using
0.5-mm Center-to-Center Spacings
description
The ’LVTH18512 and ’LVTH182512 scan test devices with 18-bit universal bus transceivers are members of
the Texas Instruments SCOPE
testability integrated-circuit family. This family of devices supports IEEE Std
1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test
circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) V
CC
operation, but with the
capability to provide a TTL interface to a 5-V system environment.
Copyright
1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.
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1CLKAB
1LEAB
1OEAB
1A1
1A2
GND
1A3
1A4
1A5
V
CC
1A6
1A7
1A8
GND
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
2A9
GND
2OEAB
2LEAB
2CLKAB
TDO
TMS
1CLKBA
1LEBA
1OEBA
1B1
1B2
GND
1B3
1B4
1B5
V
CC
1B6
1B7
1B8
GND
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2OEBA
2LEBA
2CLKBA
TDI
TCK
SN54LVTH18512, SN54LVTH182512 . . . HKC PACKAGE
SN74LVTH18512, SN74LVTH182512 . . . DGG PACKAGE
(TOP VIEW)
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