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參數(shù)資料
| 型號： | SN54LVTH182502AHV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS |
| 中文描述： | 的3.3V ABT生根粉掃描測試設備與18位通用總線收發(fā)器 |
| 文件頁數(shù)： | 15/38頁 |
| 文件大?。?/td> | 613K |
| 代理商： | SN54LVTH182502AHV |
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SCBS668C JULY 1996 REVISED JUNE 2004
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 20 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2
→
BIT 0
MSB
→
LSB
X00
DESCRIPTION
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudorandom pattern generation/36-bit mode (PRPG)
X10
Parallel-signature analysis/36-bit mode (PSA)
011
Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)
While the control input BSCs (bits 4736) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 4744 of the BSR) control the drive state (active or high impedance) of the selected
device output pins. These BCR instructions are valid only when both bytes of the device are operating in one
direction of data flow (i.e., 1OEAB
≠
1OEBA and 2OEAB
≠
2OEBA) and in the same direction of data flow (i.e.,
1OEAB
=
2OEAB and 1OEBA
=
2OEBA). Otherwise, the bypass instruction is operated.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.
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