參數(shù)資料
型號(hào)： SN54LVT8996JT
廠商： Texas Instruments, Inc.
英文描述： 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS
中文描述： 3.3 V的10位可尋址掃描港口多點(diǎn)尋址IEEE標(biāo)準(zhǔn)1149.1的JTAG技術(shù)咨詢收發(fā)器
文件頁數(shù)： 1/44頁
文件大?。?/td> 717K
代理商： SN54LVT8996JT
SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686A – APRIL 1997 – REVISED DECEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments (TI
)
Broad Family of Testability Products
Supporting IEEE Std 1149.1-1990 (JTAG)
Test Access Port (TAP) and Boundary-Scan
Architecture
Extend Scan Access From Board Level to
Higher Levels of System Integration
Promote Reuse of Lower-Level
(Chip/Board) Tests in System Environment
While Powered at 3.3 V, Both the Primary
and Secondary TAPs Are Fully 5-V Tolerant
for Interfacing to 5-V and/or 3.3-V Masters
and Targets
Switch-Based Architecture Allows Direct
Connect of Primary TAP to Secondary TAP
Primary TAP Is Multidrop for Minimal Use of
Backplane Wiring Channels
Shadow Protocols Can Occur in Any of
Test-Logic-Reset, Run-Test/Idle, Pause-DR,
and Pause-IR TAP States to Provide for
Board-to-Board Test and Built-In Self-Test
Simple Addressing (Shadow) Protocol Is
Received/Acknowledged on Primary TAP
10-Bit Address Space Provides for up to
1021 User-Specified Board Addresses
Bypass (BYP) Pin Forces
Primary-to-Secondary Connection Without
Use of Shadow Protocols
Connect (CON) Pin Provides Indication of
Primary-to-Secondary Connection
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
Support Backplane Interface at Primary and
High Fanout at Secondary
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic
Small-Outline (DW) and Thin Shrink
Small-Outline (PW) Packages, Ceramic
Chip Carriers (FK), and Ceramic DIPs (JT)
SN54LVT8996 . . . JT PACKAGE
SN74LVT8996 . . . DW OR PW PACKAGE
(TOP VIEW)
A4
A3
A2
A1
A0
BYP
GND
PTDO
PTCK
PTMS
PTDI
PTRST
A5
A6
A7
A8
A9
V
CC
CON
STDI
STCK
STMS
STDO
STRST
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
17
5
6
7
8
9
10
11
25
24
23
22
21
20
19
4
3
2
1 28
12 13 14 15 16
A8
A9
V
CC
NC
CON
STDI
STCK
A1
A0
BYP
NC
GND
PTDO
PTCK
SN54LVT8996 . . . FK PACKAGE
(TOP VIEW)
A
A
A
S
S
P
P
N
N
A
A
A
P
S
18
27 26
NC – No internal connection
description
The ’LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPE
testability
integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate
testing of complex circuit assemblies. Unlike most SCOPE
devices, the ASP is not a boundary-scannable
device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test
access port (TAP) to extend scan access beyond the board level.
Copyright
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and TI are trademarks of Texas Instruments Incorporated.
相關(guān)PDF資料
PDF描述
SN54LVT8996 3.3-V 10-Bit Addressable Scan Ports(3.3V10位可尋址掃描端口)
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SN74LVTH162240DGG 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
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