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參數(shù)資料
| 型號(hào)： | SN54LVT8996 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V 10-Bit Addressable Scan Ports(3.3V10位可尋址掃描端口) |
| 中文描述： | 3.3 V的10位尋址掃描端口（3.3V10位可尋址掃描端口） |
| 文件頁數(shù)： | 1/40頁 |
| 文件大?。?/td> | 906K |
| 代理商： | SN54LVT8996 |
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SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686 – APRIL 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of Texas Instruments Broad
Family of Testability Products Supporting
IEEE Std 1149.1-1990 (JTAG) Test Access
Port (TAP) and Boundary-Scan Architecture
Extend Scan Access From Board Level to
Higher Levels of System Integration
Promote Reuse of Lower-Level
(Chip/Board) Tests in System Environment
While Powered at 3.3 V, Both the Primary
and Secondary TAPs are Fully 5-V Tolerant
for Interfacing to 5-V and/or 3.3-V Masters
and Targets
Switch-Based Architecture Allows Direct
Connect of Primary TAP to Secondary TAP
Primary TAP Is Multidrop for Minimal Use of
Backplane Wiring Channels
Simple Addressing (Shadow) Protocol Is
Received/Acknowledged on Primary TAP
Shadow Protocols Can Occur in Any of
Test-Logic-Reset, Run-Test/Idle, Pause-DR,
and Pause-IR TAP States to Provide for
Board-to-Board Test and Built-In Self Test
10-Bit Address Space Provides for Up to
1021 User-Specified Board Addresses
Bypass (BYP) Pin Forces
Primary-to-Secondary Connection Without
Use of Shadow Protocols
Connect (CON) Pin Provides Indication of
Primary-to-Secondary Connection
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
Support Backplane Interface at Primary and
High Fanout at Secondary
Package Options Include Plastic
Small-Outline (DW) and Thin Shrink
Small-Outline (PW) Packages, Ceramic
Chip Carriers (FK), and Ceramic DIPs (JT)
description
The ’LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPE
testability
integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate
testing of complex circuit assemblies. Unlike most SCOPE
devices, the ASP is not a boundary-scannable
device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test
access port (TAP) to extend scan access beyond the board level.
These devices are functionally equivalent to the ’ABT8996 ASPs. Additionally, they are designed specifically
for low-voltage (3.3-V) V
CC
operation, but with the capability to interface to 5-V masters and/or targets.
P
Copyright
1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE is a trademark of Texas Instruments Incorporated.
17
SN54LVT8996 . . . JT PACKAGE
SN74LVT8996 . . . DW OR PW PACKAGE
(TOP VIEW)
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4
3
2
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12 13 14 15 16
A8
A9
V
CC
NC
CON
STDI
STCK
A1
A0
BYP
NC
GND
PTDO
PTCK
SN54LVT8996 . . . FK PACKAGE
(TOP VIEW)
A
A
A
S
S
P
P
N
N
A
A
A
P
S
18
27 26
A4
A3
A2
A1
A0
BYP
GND
PTDO
PTCK
PTMS
PTDI
PTRST
A5
A6
A7
A8
A9
V
CC
CON
STDI
STCK
STMS
STDO
STRST
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NC – No internal connection
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