參數(shù)資料
型號: SN54LVC74AFK
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
中文描述: 雙上升沿觸發(fā)的,有清除和預(yù)設(shè)功能的D型觸發(fā)器
文件頁數(shù): 1/9頁
文件大?。?/td> 130K
代理商: SN54LVC74AFK
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Inputs Accept Voltages to 5.5 V
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and DIPs (J)
description
The SN54LVC74A dual positive-edge-triggered
D-type flip-flop is designed for 2.7-V to 3.6-V V
CC
operation and the SN74LVC74A dual positive-
edge-triggered D-type flip-flop is designed for
1.65-V to 3.6-V V
CC
operation.
A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the
levels of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN54LVC74A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74LVC74A is characterized for operation from –40
°
C to 85
°
C.
Copyright
1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54LVC74A . . . J OR W PACKAGE
SN74LVC74A . . . D, DB, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1
1
N
2
2
V
2
1
G
N
SN54LVC74A . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
相關(guān)PDF資料
PDF描述
SN54LVC74AJ DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVC74AW DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54LVT125FK 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DB 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN54LVT125J 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
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