參數(shù)資料
型號(hào): SN54LVC74AFK
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
中文描述: 雙上升沿觸發(fā)的,有清除和預(yù)設(shè)功能的D型觸發(fā)器
文件頁(yè)數(shù): 5/9頁(yè)
文件大?。?/td> 130K
代理商: SN54LVC74AFK
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
SN74LVC74A
VCC = 1.8 V
±
0.15 V
VCC = 2.5 V
±
0.2 V
VCC = 2.7 V
VCC = 3.3 V
±
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
83
100
MHz
tw
Pulse duration
PRE or CLR low
3.3
3.3
ns
CLK high or low
3.3
3.3
tsu
Setup time before CLK
Data
3.4
3
ns
PRE or CLR inactive
2.2
2
th
Hold time, data after CLK
This information was not available at the time of publication.
1
0
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC74A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.7 V
VCC = 3.3 V
±
0.3 V
UNIT
MIN
MAX
MIN
MAX
fmax
83
100
MHz
td
tpd
CLK
Q or Q
6
1
5.2
ns
PRE or CLR
6.4
1
5.4
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC74A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
±
0.15 V
VCC = 2.5 V
±
0.2 V
VCC = 2.7 V
VCC = 3.3 V
±
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fmax
83
100
MHz
tpd
CLK
Q or Q
6
1
5.2
ns
PRE or CLR
6.4
1
5.4
tsk(o)
1
ns
This information was not available at the time of publication.
Skew between any two outputs of the same package switching in the same direction
operating characteristics, T
A
= 25
°
C
PARAMETER
TEST
CONDITIONS
VCC = 1.8 V
±
0.15 V
VCC = 2.5 V
±
0.2 V
VCC = 3.3 V
±
0.3 V
UNIT
TYP
TYP
TYP
Cpd
This information was not available at the time of publication.
Power dissipation capacitance per flip-flop
f = 10 MHz
27
pF
相關(guān)PDF資料
PDF描述
SN54LVC74AJ DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
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