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參數(shù)資料
| 型號(hào)： | SN54LV4052AW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal D-Type Flip-Flop; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18 |
| 中文描述： | 雙4通道模擬多路復(fù)用器/解復(fù)用器 |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大?。?/td> | 558K |
| 代理商： | SN54LV4052AW |
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SCLS429H MAY 1999 REVISED APRIL 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V
±
0.2 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
TEST
TA = 25
°
C
TYP
SN54LV4052A
MIN
SN74LV4052A
MIN
UNIT
(OUTPUT)
CONDITIONS
MIN
MAX
MAX
MAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation
delay time
COM or Y
Y or COM
CL = 15 pF,
(see Figure 4)
1.9
10
16
16
ns
Enable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
8
18
23
23
ns
Disable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
8.3
18
23
23
ns
Propagation
delay time
COM or Y
Y or COM
CL = 50 pF,
(see Figure 4)
3.8
12
18
18
ns
Enable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
9.4
28
35
35
ns
Disable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
12.4
28
35
35
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
TEST
TA = 25
°
C
TYP
SN54LV4052A
MIN
SN74LV4052A
MIN
UNIT
(OUTPUT)
CONDITIONS
MIN
MAX
MAX
MAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation
delay time
COM or Y
Y or COM
CL = 15 pF,
(see Figure 4)
1.2
6
10
10
ns
Enable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
5.7
12
15
15
ns
Disable
delay time
INH
COM or Y
CL = 15 pF,
(see Figure 5)
6.6
12
15
15
ns
Propagation
delay time
COM or Y
Y or COM
CL = 50 pF,
(see Figure 4)
2.5
9
12
12
ns
Enable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
6.7
20
25
25
ns
Disable
delay time
INH
COM or Y
CL = 50 pF,
(see Figure 5)
9.5
20
25
25
ns
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