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參數(shù)資料
| 型號： | SN54LV273A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR |
| 中文描述： | 八路D型倒裝，沒有明確的觸發(fā)器 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 516K |
| 代理商： | SN54LV273A |
SCLS399J APRIL 1998 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These devices are positive-edge-triggered flip-flops with direct clear (CLR) input. Information at the data (D)
inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time
of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has
no effect at the output.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
CLR
CLK
D
L
X
↑
↑
L
X
L
H
H
H
H
L
L
H
X
Q0
logic diagram (positive logic)
CLK
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D
5Q
6D
6Q
7D
7Q
8D
8Q
CLR
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
11
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54LV273AFK | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR |
| SNJ54LV273AFK | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR |
| SN54LV273AJ | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR |
| SNJ54LV273AJ | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR |
| SN74LV273ANS | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR |
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