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參數(shù)資料
| 型號： | SN54LV273 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal D-Type Flip-Flops(八D觸發(fā)器(帶清除)) |
| 中文描述： | 八路D類正反器（八?觸發(fā)器（帶清除）） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 183K |
| 代理商： | SN54LV273 |
SN54LV273, SN74LV273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS195B – FEBRUARY 1993 – REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) 2-
μ
Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC,
T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
, T
A
= 25
°
C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These octal D-type flip-flops are designed for
2.7-V to 5.5-V V
CC
operation.
The ’LV273 are positive-edge-triggered flip-flops
with direct clear (CLR) input. Information at
the data (D) inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input
is at either the high or low level, the D-input signal
has no effect at the output.
The SN74LV273 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV273 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74LV273 is characterized for operation from –40
°
C to 85
°
C.
Copyright
1996, Texas Instruments Incorporated
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54LV273 . . . J OR W PACKAGE
SN74LV273 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1
1
C
5
5
8
4
G
C
V
C
SN54LV273 . . . FK PACKAGE
(TOP VIEW)
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