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參數(shù)資料
| 型號： | SN54LV373 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal D-Type Latches(八D鎖存器(三態(tài)輸出)) |
| 中文描述： | 八路D類閥門（八?鎖存器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 166K |
| 代理商： | SN54LV373 |
SN54LV373, SN74LV373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS196C – FEBRUARY 1993 – REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) 2-
μ
Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
, T
A
= 25
°
C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These octal transparent D-type latches are
designed for 2.7-V to 5.5-V V
CC
operation.
While the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN74LV373 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV373 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74LV373 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
D
H
H
L
H
L
L
L
L
X
Q0
Z
H
X
X
Copyright
1996, Texas Instruments Incorporated
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1
1
O
5
5
V
8
4
G
L
SN54LV373 . . . FK PACKAGE
(TOP VIEW)
SN54LV373 . . . J OR W PACKAGE
SN74LV373 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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| SN54LV374 | Octal D-Type Flip-Flops(八D觸發(fā)器(三態(tài)輸出)) |
| SN54LV541A | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN74LV541ADB | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN74LV541ADGV | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN54LV541AFK | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
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