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參數(shù)資料
| 型號： | SN54HCT573A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal D-Type Latches(八D鎖存器(三態(tài)同相輸出)) |
| 中文描述： | 八路D類閥門（八?鎖存器（三態(tài)同相輸出）） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 155K |
| 代理商： | SN54HCT573A |
SN54HCT573A, SN74HCT573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS176A – MARCH 1984 – REVISED JANUARY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Inputs Are TTL-Voltage Compatible
High-Current 3-State Outputs Drive Bus
Lines Directly or up to 15 LSTTL Loads
Bus-Structured Pinout
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These octal transparent D-type latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing
buffer
bidirectional bus drivers, and working registers.
registers,
I/O
ports,
While the latch-enable (LE) input is high, the
Q outputs respond to the data (D) inputs. When
LE is low, the outputs are latched to retain the data
that was set up.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54HCT573A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74HCT573A is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each latch)
INPUTS
LE
OUTPUT
Q
OE
D
L
H
H
H
L
H
L
L
L
L
X
Q0
Z
H
X
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2
1
O
8
7
V
1
8
G
L
SN54HCT573A . . . FK PACKAGE
(TOP VIEW)
SN54HCT573A . . . J OR W PACKAGE
SN74HCT573A . . . DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
Copyright
1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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