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參數(shù)資料
| 型號： | SN54F175FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
| 中文描述： | 翻兩番D型倒裝，沒有明確的觸發(fā)器 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 72K |
| 代理商： | SN54F175FK |
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993
2–4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25
°
C
′
F175
MIN
SN54F175
SN74F175
UNIT
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
0
100
0
100
0
100
MHz
CLK high
4
4
4
tw
Pulse duration
CLK low
5
5
5
ns
CLR low
5
5
5
tsu
Setup time, data before CLK
↑
Setup time, inactive state, data before CLK
↑
Hold time, data after CLK
↑
Inactive-state setup time is also referred to as recovery time.
High or low
3
3
3
ns
CLR high
5
5
5
th
High or low
1
1
1
ns
switching characteristics (see Note 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500
,
TA = 25
°
C
′
F175
MIN
100
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
SN54F175
UNIT
SN74F175
TYP
140
MAX
MIN
100
MAX
MIN
100
MAX
fmax
tPLH
tPHL
tPLH
tPHL
MHz
CLK
Q or Q
3.2
4.6
6.5
2.7
8.5
3.2
7.5
ns
3.2
6.1
8.5
3.2
10.5
3.2
9.5
CLR
Q
3.2
6.1
8.5
3.2
10
3.2
9
ns
Q
3.7
8.6
11.5
3.7
15
3.7
13
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
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