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參數(shù)資料
| 型號(hào)： | SN54F175J |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
| 中文描述： | 翻兩番D型倒裝，沒(méi)有明確的觸發(fā)器 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | SN54F175J |
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993
Copyright
1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Contain Four Flip-Flops With Double-Rail
Outputs
Buffered Clock and Direct Clear Inputs
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These monolithic, positive-edge-triggered flip-
flops utilize TTL circuitry to implement D-type
flip-flop logic with a direct clear (CLR) input.
Information at the data (D) inputs meeting setup
time requirements is transferred to outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input
is at either the high or low level, the D-input signal
has no effect at the output.
The SN54F175 is characterized for operation over
the full military temperature range of –55
°
C to
125
°
C. The SN74F175 is characterized for
operation from 0
°
C to 70
°
C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
CLK
D
Q
Q
L
X
↑
↑
L
X
L
H
H
H
H
L
H
L
L
H
H
X
Q0
Q0
SN54F175 . . . J PACKAGE
SN74F175 . . . D OR N PACKAGE
(TOP VIEW)
SN54F175 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4Q
4D
NC
3D
3Q
1Q
1D
NC
2D
2Q
1
C
N
C
3
V
4
2
G
N
C
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
V
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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