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參數(shù)資料
| 型號： | SN54CDC586 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V Phase-Lock-Loop Clock Drivers(3.3V鎖相環(huán)時鐘驅(qū)動器(三態(tài)輸出)) |
| 中文描述： | 3.3 - V相位鎖相環(huán)時鐘驅(qū)動器（3.3鎖相環(huán)時鐘驅(qū)動器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SN54CDC586 |
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Low Output Skew for Clock-Distribution
and Clock-Generation Applications
Operates at 3.3-V V
CC
Distributes One Clock Input to Twelve
Outputs
Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency
No External RC Network Required
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
Application for Synchronous DRAM,
High-Speed Microprocessor
TTL-Compatible Inputs and Outputs
Outputs Drive Parallel 50-
Terminated
Transmission Lines
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
Distributed V
CC
and Ground Pins Reduce
Switching Noise
Packaged in 56-Pin Ceramic Flat Package
description
The SN54CDC586 is a high-performance,
low-skew, low-jitter clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the clock output signals to
the clock input (CLKIN) signal. It is specifically
designed for use with popular microprocessors
operating at speeds from 50 MHz to 100 MHz, or
down to 25 MHz on outputs configured as
half-frequency outputs. The SN54CDC586
operates at 3.3-V V
CC
and is designed to drive a
properly terminated 50- transmission line.
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to CLKIN. One of
the 12 output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input
and the outputs. The output used as the feedback pin is synchronized to the same frequency as the CLKIN input.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs
(SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN
frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output-signal duty cycles are
adjusted to 50%, independent of the duty cycle at CLKIN.
NC
AV
CC
AGND
FBIN
AGND
SEL0
SEL1
GND
GND
1Y1
V
CC
GND
1Y2
V
CC
GND
1Y3
V
CC
GND
GND
2Y1
V
CC
GND
2Y2
V
CC
GND
2Y3
V
CC
NC
NC
CLKIN
NC
AV
CC
OE
TEST
CLR
V
CC
4Y3
GND
V
CC
4Y2
GND
V
CC
4Y1
GND
GND
V
CC
3Y3
GND
V
CC
3Y2
GND
V
CC
3Y1
GND
GND
NC
WD PACKAGE
(TOP VIEW)
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NC – No internal connection
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC-
ΙΙ
B is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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