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參數(shù)資料
| 型號： | SN54F166A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Parallel-Load 8-Bit Shift Registers(并行載入8位移位寄存器) |
| 中文描述： | 并聯(lián)負載8位移位寄存器（并行載入8位移位寄存器） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 143K |
| 代理商： | SN54F166A |
SN54F166A, SN74F166A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDFS032A – D3213, JANUARY 1989 – REVISED OCTOBER 1993
Copyright
1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Synchronous Load
Direct Overriding Clear
Parallel-to-Serial Conversion
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
The
′
F166A parallel-in or serial-in, serial-out
registers feature gated clock (CLK INH and CLK)
inputs and an overriding clear (CLR) input. The
parallel-in or serial-in modes are established by
the shift/load (SH/LD) input. When high, this input
enables the serial data input and couples the eight
flip-flops for serial shifting with each clock pulse.
When low, the parallel (broadside) data inputs are
enabled, and synchronous loading occurs on the
next clock pulse. During parallel loading, serial
data flow is inhibited.
Clocking is accomplished on the low-to-high-level
edge of the clock pulse through a two-input
positive OR gate, permitting one input to be used
as a clock-enable or clock-inhibit function. Holding
either of the clock inputs high inhibits clocking;
holding either low enables the other clock input.
This allows the system clock to be free-running,
and the register can be stopped on command with
the other clock input. The clock inhibit input should
be changed to the high level only when the clock
input is high. The direct clear (CLR) overrides all
other inputs, including the clock, and resets all
flip-flops to zero.
The SN54F166A is characterized for operation
over the full military temperature range of –55
°
C
to 125
°
C. The SN74F166A is characterized for
operation from 0
°
C to 70
°
C.
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
QA
L
OUTPUT
QH
CLR
SH/LD
CLK INH
CLR
SER
PARALLEL
A . . . H
QB
L
L
X
X
X
X
X
L
H
X
L
L
↑
↑
↑
↑
X
X
QA0
a
QB0
b
QH0
h
H
L
L
X
a . . . h
H
H
L
H
X
H
QAn
QAn
QB0
QGn
QGn
QH0
H
H
L
L
X
L
H
X
H
X
X
QA0
The CLK INH input was taken to the high level in a prior configuration when CLK was high.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SER
A
B
C
D
CLK INH
CLK
GND
V
CC
SH/LD
H
Q
H
G
F
E
CLR
SN54F166A . . . J PACKAGE
SN74F166A . . . D OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
H
Q
H
NC
G
F
B
C
NC
D
CLK INH
SN54F166A . . . FK PACKAGE
(TOP VIEW)
A
S
N
C
E
V
S
C
G
N
NC – No internal connection
C
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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