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參數(shù)資料
| 型號： | SN54AS533 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal D-Type Latches(八D鎖存器(三態(tài)輸出)) |
| 中文描述： | 八路D類閥門（八?鎖存器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 126K |
| 代理商： | SN54AS533 |
SN54AS533, SN74AS533A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS254A – APRIL 1982 – REVISED JUNE 1992
Copyright
1992, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
8 Latches in a Single Package
3-State Bus-Driving Inverting Outputs
Full Parallel Access for Loading
Buffered Output-Enable Inputs
P-N-P Inputs Reduce DC Loading on Data
Lines
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These 8-bit D-type transparent latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for imple-
menting buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q
outputs follow the complements of the data (D)
inputs. When LE is taken low, the Q outputs are
latched at the inverse level set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic level) or a high-impedance
state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The output-enable (OE) input does not affect internal operations of the latch. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN54AS533 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74AS533A is characterized for operation from 0
°
C to 70
°
C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Q
L
H
Q0
Z
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54AS533 . . . J PACKAGE
SN74AS533A . . . DW OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
SN54AS533 . . . FK PACKAGE
(TOP VIEW)
1
1
O
5
5
8
4
G
L
V
C
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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相關(guān)代理商/技術(shù)參數(shù) |
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