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參數(shù)資料
| 型號(hào)： | SN54AS32FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE 2-INPUT POSITIVE-OR GATES |
| 中文描述： | 四2輸入陽性或門 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 84K |
| 代理商： | SN54AS32FK |
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDAS113B – APRIL 1982 – REVISED DECEMBER 1994
Copyright
1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain four independent 2-input
positive-OR gates. They perform the Boolean
functions Y = A
B or Y = A + B in positive logic.
The
characterized for operation over the full military
temperature range of –55
°
C to 125
°
C. The
SN74ALS32 and SN74AS32 are characterized for
operation from 0
°
C to 70
°
C.
SN54ALS32
and
SN54AS32
are
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
H
B
X
H
X
H
H
L
L
L
logic symbol
logic diagram (positive logic)
1
1A
2
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
≥
1
1Y
3
2Y
6
3Y
8
4Y
11
1
1A
2
1B
1Y
3
4
2A
5
2B
2Y
6
9
3A
10
3B
3Y
8
12
4A
13
4B
4Y
11
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
SN54ALS32, SN54AS32 . . . J PACKAGE
SN74ALS32, SN74AS32 . . . D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
SN54ALS32, SN54AS32 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1
1
N
3
3
V
4
2
N
C
NC – No internal connection
G
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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