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| 型號： | SN54AS194J |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | SN54AS181B SN74AS181A |
| 中文描述： | SN54AS181B SN74AS181A |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 123K |
| 代理商： | SN54AS194J |
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
MODE
CLK
SERIAL
PARALLEL
QA
QB
QC
QD
S1
S0
LEFT
RIGHT
A
B
C
D
L
X
X
X
X
X
X
X
X
X
L
L
L
L
H
X
X
L
↑
↑
↑
↑
↑
X
X
X
X
X
X
X
QA0
a
QB0
b
QC0
c
QD0
d
H
H
H
X
X
a
b
c
d
H
L
H
X
H
X
X
X
X
H
QAn
QAn
QCn
QCn
QB0
QBn
QBn
QDn
QDn
QC0
QCn
QCn
H
H
L
H
X
L
X
X
X
X
L
H
H
L
H
X
X
X
X
X
QBn
QBn
QA0
H
H
L
L
X
X
X
X
X
L
H
L
L
X
X
X
X
X
X
QD0
H = high level (steady state); L = low level (steady state); X = irrelevant (any input, including transitions);
↑
= transition from
low to high level; a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively; QA0, QB0, QC0, QD0 = the
level of QA, QB, QC, or QD, respectively, before the ndicated steady-state nput conditions were established; QAn, QBn, QCn,
QDn = the level of QA, QB, QC, respectively, before the most recent
↑
transition of the clock.
logic symbol
SRG4
0
3
3, 4D
4
B
3, 4D
5
C
3, 4D
6
D
2, 4D
7
SL SER
1, 4D
2
SR SER
3, 4D
3
A
R
0
1
9
11
CLK
C4
1 /2
M
14
13
15
1
10
S1
S0
12
CLR
QA
QB
QC
QD
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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