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參數(shù)資料
| 型號： | SN54AS194J |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | SN54AS181B SN74AS181A |
| 中文描述： | SN54AS181B SN74AS181A |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 123K |
| 代理商： | SN54AS194J |
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
Copyright
1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Parallel-to-Serial, Serial-to-Parallel
Conversions
Left or Right Shifts
Parallel Synchronous Loading
Direct Overriding Clear
Temporary Data-Latching Capability
Package Options Include Plastic
Small-Outline Packages (D), Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These 4-bit bidirectional universal shift registers
feature parallel outputs, right-shift and left-shift
serial (SR SER, SL SER) inputs, operating-
mode-control (S0, S1) inputs, and a direct
overriding clear (CLR) line. The registers have
four distinct modes of operation:
Inhibit clock (temporary data latch/do nothing)
Shift right (in the direction Q
A
toward Q
D
)
Shift left (in the direction Q
D
toward Q
A
)
Parallel (broadside) load
Parallel synchronous loading is accomplished by
applying the four bits of data and taking both S0
and S1 high. The data is loaded into the
associated flip-flops and appears at the outputs
after the positive transition of the clock (CLK)
input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left
synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when
both mode-control inputs are low.
The SN54AS194 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74AS194 is characterized for operation from 0
°
C to 70
°
C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
SR SER
A
B
C
D
SL SER
GND
V
CC
Q
A
Q
B
Q
C
Q
D
CLK
S1
S0
SN54AS194 . . . J PACKAGE
SN74AS194 . . . D OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Q
B
Q
C
NC
Q
D
CLK
A
B
NC
C
D
S
C
N
S
S
S
G
N
NC – No internal connection
V
Q
SN54AS194 . . . FK PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54AS195 | 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| SN54AS373FK | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54ALS373FK | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54AS374FK | OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN54ALS374AFK | OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
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