參數(shù)資料
型號(hào): SN54ABT18652
廠商: Texas Instruments, Inc.
英文描述: SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS
中文描述: 掃描測(cè)試設(shè)備與18位總線收發(fā)器和寄存器
文件頁數(shù): 1/11頁
文件大小: 169K
代理商: SN54ABT18652
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
SCOPE
Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, and
P1149.1A CLAMP and HIGHZ
– Parallel Signature Analysis at Inputs With
Masking Option
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
Packaged in 64-Pin Plastic Shrink Quad Flat
Pack (PM) and 68-Pin Ceramic Quad Flat
Pack (HV)
Copyright
1992, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
SCOPE
Family of Testability Products
Members of the Texas Instruments
Widebus
Family
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
Include D-Type Flip-Flops and Control
Circuitry to Provide Multiplexed
Transmission of Stored and Real-Time Data
Two Boundary-Scan Cells per I/O for
Greater Flexibility
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
1B4
1B5
1B6
GND
1B7
1B8
1B9
V
CC
NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
NC
V
CC
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
N
T
1
1
1
1
G
1
1
T
N
T
2
2
2
G
2
2
2
T
2
2
1
1
G
2
2
2
G
1
1
1
19 20
51
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49
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35
21
1
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67 66 65 64 63
68
62
60 59 58
61
26 27 28 29 30
57 56
18
55 54 53 52
31 32 33 34
SN54ABT18652 . . . HV PACKAGE
(TOP VIEW)
C
V
C
NC – No internal connection
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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