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參數(shù)資料
| 型號： | SN54ABT18502A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Scan Test Devices With 18-Bit Universal Bus Transceivers(掃描測試裝置(帶18位通用總線收發(fā)器)) |
| 中文描述： | 掃描測試設(shè)備與18位通用總線收發(fā)器（掃描測試裝置（帶18位通用總線收發(fā)器）） |
| 文件頁數(shù)： | 6/35頁 |
| 文件大?。?/td> | 738K |
| 代理商： | SN54ABT18502A |
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SN54ABT18502A, SN54ABT182502A, SN74ABT18502A, SN74ABT182502A
SCAN TEST DEVICES WITH
18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS488 – AUGUST 1994
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
test architecture
Serial test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial test bus. The
TAP controller monitors two signals from the test bus, namely TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated,
the device contains an 8-bit instruction register and four test data registers: a 48-bit boundary-scan register, a
3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device identification register.
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Update-DR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = L
TMS = H
TMS = L
Exit2-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Update-IR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
Exit2-IR
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
Figure 1. TAP Controller State Diagram
P
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