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| 型號： | SMJ4C1024-10SV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 1048576 1位動態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 5/27頁 |
| 文件大?。?/td> | 403K |
| 代理商： | SMJ4C1024-10SV |
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SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
address (A0–A9) (continued)
of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row
decoder. CAS is used as a chip select to activate the output buffer as well as to latch the address bits into the
column-address buffer.
write enable (W)
The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic
low selects the write mode. The write-enable pin can be driven from standard TTL circuits without a pullup
resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS (early write),
data out remains in the high-impedance state for the entire cycle, permitting common input/output operation.
data in (D)
Data-in is written during a write or a read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip latch. In an early-write cycle, W is brought low prior to CAS,
and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or a
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold times
referenced to this signal.
data out (Q)
The 3-state output buffers provide direct TTL compatibility (no pullup resistor required) with a fanout of two
series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS is brought low. In a read cycle, the output becomes valid after the access time t
a(C)
. The access time
from CAS low (t
a(C)
) begins with the negative transition of CAS as long as t
a(R)
and t
a(CA)
are satisfied. The output
becomes valid after the access time has elapsed and remains valid while CAS is low; when CAS goes high, the
output returns to a high-impedance state. In a delayed-write or read-modify-write cycle, the output follows the
sequence for the read cycle.
refresh
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 512 rows (A0–A8). A normal read or write cycle refreshes all bits in each selected row. A RAS-only
operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffer remains
in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. Hidden
refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS
at V
IL
after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh
cycle.
CAS-before-RAS (CBR) refresh
CBR refresh is used by bringing CAS low earlier than RAS (see parameter t
d(CLRL)R
) and holding it low after
RAS falls (parameter t
d(RLCH)R
). For successive CBR refresh cycles, CAS can remain low while cycling RAS.
The external address is ignored and the refresh address is generated internally. The external address is also
ignored during the hidden refresh cycles.
power up
To achieve proper device operation, an initial pause of 200
μ
s followed by a minimum of eight initialization cycles
is required after full V
CC
level is achieved.
test function (TF) pin
During normal device operation, TF must be disconnected or biased at a voltage
≤
V
CC
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ4C1024-12FQ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| SMJ4C1024-12HJ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| SMJ4C1024-12HK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| SMJ4C1024-12HL | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| SMJ4C1024-12JD | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY |
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